Electrical fuses (eFuses) are used to reprogram integrated circuit chips, such computer chips. For example, eFuses can be used to provide in-chip performance tuning. If a sub-system fails, for example, an eFuse can be blown to change behavior or to switch in a back-up system. A chip may be provided with an array of eFuse cells. An approach known to the applicant is the 1T1R eFuse architecture where each eFuse cell includes an NMOS program transistor (1T) and a fuse element (1R). The layout of the 1T1R eFuse cell structure makes it very difficult to reduce the overall area of the eFuse array. For example, the fuse elements of this architecture are located in the metal 2 (M2) layer of the integrated circuit, which is subject to strict design rule check (DRC) constraints that define, for example, all metal line minimum and maximum widths and metal line spacing, amongst other rules. These constraints mean that the eFuse area can't simply be reduced by reducing the fuse size (i.e., metal line width) or spacing (i.e., between fuse lines). Further, within an array of eFuses, all eFuses in the same column of fuse cells are connected to and share the same bit line through which the programming current is provided. This arrangement leads to a larger resistance in the program path, which reduces the programming current.